verilog code for full adder
design.v module half_adder(sum,carry,a,b); input a,b; output sum,carry; xor (sum,a,b); and (carry,a,b); endmodule module fa(fsum,fcarry,a,b,c); input a,b,c; output fsum,fcarry; wire sum1,carry1,carry2; half_adder ha1(sum1,carry1,a,b); half_adder ha2(fsum,carry2,sum1,c); or(fcarry,carry1,carry2); endmodule testbench.v // Code your testbench here // or browse Examples module andtest; reg a1, b1; wire y1; andgate andtest ( .a(a1), .b(b1), .y(y1)); initial begin $monitor("a=%d b=%d y=%d",a1, b1, y1); a1 = 1'b0; b1 = 1'b0; #5 a1 = 1'b0; b1 = 1'b1; #5 a1 = 1'b1; b1 = 1'b0; #5 a1 = 1'b1; b1 = 1'b1; end i...